How To Upload Verilog To Github

Verilog Format

Console awarding for apply format to verilog file.

sample

How to use

Application options:

              usage: [java -jar verilog-format.jar|./verilog-format|verilog-format.exe]        [-f <pathname>] [-h] [-p] [-s <verilog-format.backdrop>] [-v]  -f,--format <pathname>                      verilog file  -h,--help                                   print this message  -p,--print                                  print file formated  -s,--settings <verilog-format.properties>   settings config  -5,--version                                verilog-format version

Examples

                              ## Print input_file.v formatted              $ ./verilog-format -p -f input_file.v -s verilog-format.backdrop                              ## Format input_file.five              $ ./verilog-format -f input_file.v -s verilog-format.properties                              ## Format input_file.v                              ## If .verilog-format.properties exist in project binder, this is used,                              ## otherwise default setting is used..              $ ./verilog-format -f input_file.5

Install in Linux

Clone repository.

$ git clone https://github.com/ericsonj/verilog-format.git
Install verilog-format

$ cd verilog-format/bin/
$ sudo mkdir /opt/verilog-format
$ sudo unzip verilog-format-LINUX.nada -d /opt/verilog-format/
Execute like java

$ java -jar /opt/verilog-format/verilog-format.jar
Execute similar linux script

$ /opt/verilog-format/verilog-format
Install in organisation

$ sudo cp /opt/verilog-format/verilog-format /usr/bin/

Install in Windows

Clone repository or download verilog-format-WIN.zip
Unzip and copy in your preferer folder.

Build projection

For build de projection, Maven is needed.

$ cd verilog-format
$ mvn clean parcel
$ ls target/

Verilog-Format Style Options

This options are setting in .verilog-format.backdrop file.

Example

                              ## File .verilog-format.properties              IndentWidth=4              IndentType=space              SpacesBeforeTrailingComments=0              SpacesAfterTrailingComments=0              AlignLineComments=true              AlignNoBlockingAssignments=true              AlignBlockingAssignments=truthful              SpacesInParentheses=false              SpacesInSquareBrackets=false

IndentWidth=[number]

                              //                IndentWidth=four  #(default)              always              @(posedge              clk)              if              (load              ==              ane)         bitc              <=              0;              else              if              (load              ==              0              &&              clk_baud              ==              one)         bitc              <=              bitc              +              1;                              //                IndentWidth=1              always              @(posedge              clk)              if              (load              ==              ane)   bitc              <=              0;              else              if              (load              ==              0              &&              clk_baud              ==              1)   bitc              <=              bitc              +              1;

IndentType=[space|tab]

                              //                IndentType=infinite  #(default)              always              @(posedge              clk)              if              (load              ==              1)         bitc              <=              0;              else              if              (load              ==              0              &&              clk_baud              ==              1)         bitc              <=              bitc              +              one;                              //                IndentType=tab  #  non recommended all the same              ever              @(posedge              clk)              <tab>              if              (load              ==              ane)              <tab><tab>bitc              <=              0;              <tab>              else              if              (load              ==              0              &&              clk_baud              ==              i)              <tab><tab>bitc              <=              bitc              +              1;

SpacesInParentheses=[true|faux]

                              //                SpacesInParentheses=imitation  #(default)              always              @(posedge              clk)              if              (load              ==              1)                              //                SpacesInParentheses=true              always              @(              posedge              clk )              if              ( load              ==              1              )

SpacesInSquareBrackets=[true|false]

                              //                SpacesInSquareBrackets=false  #(default)              reg              [DW-              ane:0] rom [0:NPOS-              one];              always              @(posedge              clk)              begin              data              <=              rom[addr];              end                              //                SpacesInSquareBrackets=true              reg              [ DW-              1:0              ] rom [              0:NPOS-              one              ];              always              @(posedge              clk)              begin              information              <=              rom[ addr ];

AlignBlockingAssignments=[true|false]

                              //                AlignBlockingAssignments=truthful  #(default)              assign              load              =              (state              ==              Commencement) ?              1              :              0;              assign              baud_en              =              (land              ==              IDLE) ?              0              :              ane;                              //                AlignBlockingAssignments=imitation              assign              load              =              (state              ==              Start) ?              1              :              0;              assign              baud_en              =              (state              ==              IDLE) ?              0              :              ane;

AlignNoBlockingAssignments=[true|faux]

                              //                AlignNoBlockingAssignments=true  #(default)              state_ts              <=              IDLE; state_pad              <=              IDLE; state_wait              <=              IDLE;                              //                AlignNoBlockingAssignments=fake              state_ts              <=              IDLE; state_pad              <=              IDLE; state_wait              <=              IDLE;

AlignLineComments=[true|simulated]

                              //                AlignLineComments=fake  #(default)              e'er              @(posedge              clk)                              //                always              if              (load              ==              1)                              //                if              bitc              <=              0;                              //                            else              if              (load              ==              0              &&              clk_baud              ==              ane)                              //                else if              bitc              <=              bitc              +              ane;                              //                                            //                AlignLineComments=true              always              @(posedge              clk)                              //                ever              if              (load              ==              1)                              //                if              bitc              <=              0;                              //                            else              if              (load              ==              0              &&              clk_baud              ==              1)                              //                else if              bitc              <=              bitc              +              1;                              //

SpacesBeforeTrailingComments=[number]

                              //                SpacesBeforeTrailingComments=one  #(default)              localparam              IDLE              =              0;                              //IDLE                              //                SpacesBeforeTrailingComments=0              localparam              IDLE              =              0;                //IDLE

SpacesAfterTrailingComments=[number]

                              //                SpacesAfterTrailingComments=0  #(default)              localparam              IDLE              =              0;                              //IDLE                              //                SpacesAfterTrailingComments=iii              localparam              IDLE              =              0;                              //                IDLE